The IP cores are written on Verilog, they do to have a VHDL instantiation template. I spent way too long getting things to work in my project. They all worked perfect in the demo project.

Data changing at 100Mhz, We are supplying 32 bits each time. The SDRAM is at 200Mhz writing 16 bits at a time. 

We put s_we high as we wish to write, its not writing till s_wr_ack. So keep the address and data the same, change on the next cycle, cycle though addresses and data.

Last write we need to assert s_last

When reading it back we do similar, the s_last on the last read. However out data is delayed coming out, as it takes time to get the data back. So we looks at s_rd_valid. This would be an ideal write signals for a Fifo.

Attached is a zip up of the project. There are still debug signals in there so its easy to see the Read/Writes happening.