I have a couple of projects coming up where HDMI needs to be put into memory. One of them due to be HD(1920×1080) it would be an average write speed of 24bits@124Mhz. The SDRAM cannor achieve this, can 32bits@100Mhz or 16bits@200Mhz max(o course you need to leave room for some averheads) So one project will need to be DDR.

The project that will e using SDRAM like on the T20BGA256 dev board is storing around 512×256 pixels, so with FIFO’s we have enough bandwidth.

The HDMI will write to the SDRAM, and SDRAM is read out to go to the LED module(s). I would like to do some test patterns from the Sapphire Core. These dont need to be 60fps. They can be dran in another buffer and page pointer swapped so the new image gets displayed.

So far I have used SPI to from from the Sapphire core to the Logic. This would work, not high speed though. I’d like to explore AXI. I have used AXI on the Xilinx Zynq. I’d need to create an AXI mux, as there is effectivly 3 things that want to connect to SDRAM. ith Sapphire working at 50Mhz, and HDMI writing at 100Mhz, and LED module reading at 100Mhz. There are two speed of AXI. Nee to take care on handling that. Clock domain crosings using extra logic. Perhap the SPI although slower would be cleaner and less logic.

To be continued….